PROFIBUS DP Slave for Intel FPGA

Integration of PROFIBUS DP into Field Devices using Intel (Altera) FPGA

The PROFIBUS DP Slave IP Core and the protocol software executed inside the FPGA comprise all digital functions required for implementing a PROFIBUS DP slave. Thus, no specific fieldbus controller ASIC is needed in addition.

Minimum Development Effort

  • Combination of all components required for implementing a PROFIBUS DP Slave into a Field Programmable Gate Array (FPGA)
  • PROFIBUS DP bus control logic implemented as loadable IP Core
  • PROFIBUS DP protocol stack ready to be used on soft core processor within FPGA
  • Including PROFIBUS versions DP (exchange of cyclic data and diagnosis) and DP-V1 (acyclic data exchange and extended diagnosis)

One API For Quick Integration

  • Simple Device Application Interface (SDAI) designed as efficient protocol abstraction layer to use different protocols with same application
  • PROFIBUS, PROFINET IRT, EtherCAT, EtherNet/IP, POWERLINK and Modbus TCP using the same API
  • Device application software running on second processor inside the FPGA or on separate external host processor

Space-saving and future-proof implementation

  • Provision of complete bus control logic for accessing PROFIBUS DP network
  • Handling of all time-critical parts of PROFIBUS DP Data Link Layer and cyclic data exchange
  • No dependency on fieldbus controller ASIC and its vendor

Flexible, scalable and low-maintenance

  • Various protocols can be used alternatively or in parallel, also with multiple channels
  • Easily extendible by customer-specific functions thanks to FPGA technology
  • Easy integration of future versions
  • Uniform license for all protocols
HardwareQSys Subsystem
  • IP Core with PROFIBUS DP bus control logic 
  • 1 Nios II IP Core for protocol processing
  • DPRAM (4 KB) interface to application
  • Memory-mapped bridges for Flash and RAM
PROFIBUS Clocks16 MHz, 84 MHz
Nios II ClockConfigurable (default: 75 MHz)
SoftwarePROFIBUS Functionality
  • Cyclic services
  • Sync / Freeze
  • Input / output data up to 244 Bytes each
  • Configuration / parameter / diagnosis data up to 244 Bytes each
  • Acyclic Read / Write (Master Class 1 and Class 2)
  • Up to 3 simultaneous Master Class 2 connections
  • Automatic baud rate recognition
  • Identification & Maintenance services (IM0)
  • Modular slave with up to 64 modules
  • Support of dynamic I/O configuration change by Slave application
  • Diagnostic alarms and Pull/Plug alarms
  • Support of redundancy switch over command
ConformityTested with PROFIBUS DP Tester Software
System RequirementsFPGA Type
FPGA Resources
Altera Cyclone IV or V (and SoC)
Approximately 5,000 ALMs, 32 M10k memory blocks
Code and initialized data: approximately 470 KB
LicensingPer Unit Base or Annual Base
ISL-YY-015320Per Unit License for One Slave Device (security EEPROM, packing unit: 250 pieces)
LAA-NN-019320Annual Product License Fee (right to sell an unlimited number of a single customer product for one year)


Scope of Delivery


IP Core
  • PROFIBUS DP Slave IP, Qsys subsystem for PROFIBUS Slave
  • FPGA sample design        
  • PROFIBUS DP slave stack, binary format
  • Sample application for "Evaluation Kit Altera Cyclone V E"
  • Sample device description file (GSD)
  • Sample projects for Siemens PLCs and Softing configurator
DocumentationPROFIBUS Slave user manual, SDAI manual (electronic format)


Additional Products and Services

SIA-NN-018101PROFIBUS DP Integration Workshop
DDA-NN-006014PROFIBUS Tester 5 (BC-700-PB)
TRA-PB-TECHPROFIBUS Technology Training

Softing Inc.