Hardware | QSys Subsystem |
|
PROFIBUS Clocks | 16 MHz, 84 MHz | |
Nios II Clock | Configurable (default: 75 MHz) | |
Software | PROFIBUS Functionality |
|
Conformity | Tested with PROFIBUS DP Tester Software | |
System Requirements | FPGA Type FPGA Resources Memory | Altera Cyclone IV or V (and SoC) Approximately 5,000 ALMs, 32 M10k memory blocks Code and initialized data: approximately 470 KB |
Licensing | Per Unit Base or Annual Base |
ISL-YY-015320 | Per Unit License for One Slave Device (security EEPROM, packing unit: 250 pieces) |
LAA-NN-019320 | Annual Product License Fee (right to sell an unlimited number of a single customer product for one year) |
IP Core |
|
Software |
|
Documentation | PROFIBUS Slave user manual, SDAI manual (electronic format) |
SIA-NN-018101 | PROFIBUS DP Integration Workshop |
DDA-NN-006014 | PROFIBUS Tester 5 (BC-700-PB) |
TRA-PB-TECH | PROFIBUS Technology Training |