Modbus TCP/IP Subsystem for Altera-Intel FPGA |
IP Core configuration | - Switch IP core with 2 external ports and 1 or 2 internal ports
- Communication CPU IP core for processing the Modbus TCP/IP protocol
- DPRAM interface to application processor (FPGA-internal or external)
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Switch clock | 125 MHz |
Supported FPGA families | Cyclone III, Cyclone IV, Cyclone V, Cyclone V SoC, Cyclone 10 LP, MAX 10 |
Functionality | - Modbus TCP/IP server compliant to Modbus TCP/IP specification
- Supported Modbus Services:
- 0x01 Read Coils
- 0x02 Read Discrete Inputs
- 0x03 Read Holding Registers
- 0x04 Read Input Registers
- 0x05 Write Single Coil
- 0x06 Write Single Register
- 0x0F Write Multiple Coils
- 0x10 Write Multiple Registers
- Assignable Standard Objects:
- VendorName
- ProductCode
- MajorMinorRevision
- ProductName
- I/O Data Size up to 1024 Bytes
- Optional 2nd internal switch port for direct connection of the application CPU
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Application Programming Interface | Simple Device Application Interface (SDAI) |