EtherNet/IP Adapter Subsystem for Altera-Intel FPGA |
IP Core configuration | - Switch IP core with 2 external ports and 1 or 2 internal ports
- Communication CPU IP core for processing the EtherNet/IP protocol
- DPRAM interface to application processor (FPGA-internal or external)
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Switch clock | 125 MHz |
Supported FPGA families | Cyclone III, Cyclone IV, Cyclone V, Cyclone V SoC, Cyclone 10 LP, MAX 10 |
Functionality | - EtherNet/IP Adapter compliant to ODVA conformance test CT-20
- Media Redundancy (Device Level Ring; announce-based and beacon-based)
- LLDP protocol
- Quality of Service (QoS) supported
- Support for Quick Connect
- Communication support for CIP Safety
- Optional 2nd internal switch port for direct connection of the application CPU
- Optional hardware acceleration (DMA)
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Cycle time | down to 100 μs |
Number of connections | - Support for up to 10 concurrent I/O Connections
- Support for up to 10 concurrent Encapsulation Sessions
- Support for at least 2 concurrent Explicit Messaging Connections (minimum guaranteed number) for each Encapsulation Session
- Support for up to 6 additional Explicit Messaging Connections to be used by any client
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Application Programming Interface | Simple Device Application Interface (SDAI) |