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PROFIBUS DP Slave Subsystem for Altera-Intel FPGA

PROFIBUS DP Slave IP Core and Communication Processor for the Integration of PROFIBUS on Altera-Intel FPGA

  • Simplifies PROFIBUS DP connectivity for field devices with Altera-Intel FPGA
  • Optimized PROFIBUS DP IP core and pre-installed software handle the entire protocol
  • PROFIBUS DP and other industrial networks are supported by the same API
  • Fast and robust operation by hardware/logic support and optional line redundancy
PROFIBUS DP Slave Subsystem for Altera-Intel FPGA

Overview

Easy-to-Integrate PROFIBUS DP Subsystem for FPGAs

  • Entire protocol is handled by pre-installed software, no need for any porting
  • Example project for fast hands-on experience
  • Adaptation to the application requirements by extensive configuration options
  • Large choice of supported FPGA families and sizes

Low Total Cost of Ownership

  • No dependency on special ASICs
  • Risk-free implementation thanks to Softing‘s consulting, integration, and pre-certification services
  • Re-configuration and extension possible even after production
  • Simple addition of further protocols

Pre-certified to Latest Standards

  • Compliant to current PROFIBUS specifications
  • Tested with current conformance test tool „PROFIBUS DP Tester“

Fast and Robust Operation

  • PROFIBUS DP IP core supports baud rates of up to 12 Mbit/s, offering fast automatic baud rate recognition
  • Device application software is separated from protocol software
  • Support for slave redundancy and optional line redundancy
  • Cycle times down to 100 μs

Technical Data

PROFIBUS DP Slave Subsystem for Altera-Intel FPGA

IP Core configuration
  • PROFIBUS DP Slave IP core
  • Communication CPU IP core for processing the PROFIBUS DP protocol
  • DPRAM interface to application processor (FPGA-internal or external)
PROFIBUS clocks 16 MHz, 84 MHz
Supported FPGA families Cyclone III, Cyclone IV, Cyclone V, Cyclone V SoC, Cyclone 10 LP, MAX 10
Functionality
  • PROFIBUS DP Slave
  • PROFIBUS DP, PROFIBUS DP-V1
  • Cyclic services
  • Sync / Freeze
  • Input / output data: up to 244 Bytes each
  • Configuration / parameter / diagnosis data: up to 244 Bytes each
  • Acyclic Read / Write (Master Class 1 and Class 2)
  • Up to 3 simultaneous Master Class 2 connections
  • Automatic baud rate recognition
  • Identification & Maintenance services (IM0)
  • Modular slave with up to 64 modules
  • Support of dynamic I/O configuration by Slave application
  • Diagnostic alarms and Pull/Plug alarms
  • Support of redundancy switch over command
  • Optional line redundancy
Cycle time down to 100 μs (minimum slave interval)
Application Programming Interface Simple Device Application Interface (SDAI)

Order Information

Scope of Delivery  
IP / Logic
  • Complete PROFIBUS DP Slave subsystem
  • Supplementary IP cores
  • Sample application FPGA design
Software
  • Ready-to-run protocol software (executable) for the PROFIBUS DP Slave subsystem
  • API library for the application processor (including source code)
  • Sample application software (including source code)
Documentation Download: PROFIBUS DP subsystem implementation guide and additional information
Order Numbers  
Please contact us for details PROFIBUS DP Slave Subsystem for Altera-Intel FPGA
We are happy to discuss your particular requirements and adequate licensing options with you.
Additional Products and Services  
SIA-YY-012501 Integration workshop for implementing PROFIBUS DP
SIA-YY-012503 Integration support provided by e-mail or phone
Please contact us for details Integration and pre-certification services
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