PROFINET Device subsystem for Altera-Intel FPGA |
IP Core configuration | - Switch IP core with 2 external ports and 1 or 2 internal ports
- Communication CPU IP core for processing the PROFINET protocol
- DPRAM interface to application processor (FPGA-internal or external)
|
Switch clock | 125 MHz |
Supported FPGA families | Cyclone III, Cyclone IV, Cyclone V, Cyclone V SoC, Cyclone 10 LP, MAX 10 |
Functionality | - PROFINET Device according to specification V2.44, Conformance Class B or C
- Media Redundancy Client (MRP or MRPD)
- Support for PROFINET Security Class I
- Support for Fast Startup (FSU)
- Support for System redundancy (S2)
- Communication support for PROFIsafe
- Optional 2nd internal switch port for direct connection of the application CPU
- Optional hardware acceleration (DMA)
|
Cycle time | down to 250 μs |
Number of controller connections | up to 4 (for shared device, S2 redundancy and supervisor connection) |
Application Programming Interface | Simple Device Application Interface (SDAI) |